1. Field of the Disclosure
The present disclosure relates generally to microelectronic packaging, three-dimensional integration (3Di), and more specifically to fabrication of stacked semiconductor chip assemblies including bonding of first and second wafer articles to one another and a method of improving chip-to-chip accuracy at the wafer-to-wafer bonding step.
2. Description of Related Art
In the semiconductor device fabrication industry, three dimensional integration (3Di) techniques may be used for integration at the component level as a packaging process or at the device/circuit level. Device/circuit level 3Di includes the combining of different substrates (i.e., wafers), each having patterned circuitry formed thereon, in a manner to form a larger device/circuit by matching appropriate circuit parts together. More specifically, two substrates are placed in contact with each other in an aligned manner, and pressure is applied to initiate the bonding of the two substrates. Semiconductor devices are typically produced in arrays on wafer substrates ranging from 1 to 18 inches in diameter. The substrates are then separated into individual devices or dies that are packaged to allow practical macro-level connection of the devices in the context of a larger circuit. As the requirements for chip density and smaller packaging form factors increase, advances have been made in three-dimensional integration of circuits. In this technology, devices are stacked and bonded in the vertical or z-direction. Typically, the stacked devices are electrically coupled by electrical contact pads on the devices or by through-silicon vias (TSVs).
A typical process for vertically integrating devices on silicon wafers is a wafer-to-wafer integration scheme in which the host wafer and donor wafer are aligned with one another, and the wafers are bonded together using oxide-oxide fusion bonding. The donor wafer is then thinned to expose TSVs that connect to the host wafer, or is thinned followed by fabrication of TSVs that connect to the host wafer. For device/circuit level 3DI applications, the alignment between the two substrates becomes critical due to the circuit connections that need to be made between the patterned circuitry within each substrate. The better the bonding alignment capability, the less misalignment tolerance that needs to be built into circuit designs and therewith the silicon area used for the integrated circuit.
For full-built device wafers, incoming chip-to-chip misalignment plays an important role and needs to be corrected. Incoming chip-to-chip misalignment comes from two major contributions: global wafer-to-wafer incoming runout, and local distortion. It is desirable to eliminate local chip-to-chip misalignment in order to achieve the highest possible chip-to-chip accuracy at the wafer-to-wafer (global) bonding step.